1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2003, 2008, 2012. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. single event radiation hardened high speed, current mode pwm is-1845asrh, IS-1845ASEH the is-1845asrh, IS-1845ASEH are designed to be used in switching power supplies operating in current- mode. the rising edge of the on-chip oscillator turns on the output. turn-off is controlled by the current sense comparator and occurs when the sensed current reaches a peak controlled by the error amplifier. constructed with intersil?s rad hard silicon gate (rsg) dielectrically isolated bicmos process, these devices are immune to single event latch-up and have been specifically designed to provide a high level of immunity to single event transients. all specified paramete rs are guaranteed and tested for 300krad(si) total dose performance at a high dose rate and 50krad(si) total dose at a low dose rate. detailed electrical specifications for these devices are contained in the smd 5962-01509 . a ?hot-link? is also provided on our website for downloading the smd. features ? electrically screened to dscc smd # 5962-01509 ? qml qualified per mil-prf-38535 requirements ? radiation environment - high dose rate. . . . . . . . . . . . . . . . . . . . .300 krad(si) (max) - low dose rate . . . . . . . . . . . . . . . . . . . . . . 50 krad(si) (max) - sel immune . . . . . . . . . . . . . . . . . . . . dielectrically isolated - seu immune. . . . . . . . . . . . . . . . . . . . . . . . 35mev/mg/cm 2 - seu cross-section at 89mev/mg/cm 2 . . . . . . 5 x 10 -6 cm 2 ? low start-up current . . . . . . . . . . . . . . . . . . . . . . . 100a (typ) ? fast propagation delay . . . . . . . . . . . . . . . . . . . . . . . 80ns (typ) ? supply voltage range . . . . . . . . . . . . . . . . . . . . . . . 12v to 20v ? high output drive. . . . . . . . . . . . . . . . . . . . . . . . 1a (peak, typ) ? undervoltage lockout . . . . . 8.8v start (typ), 8.2v stop (typ) applications ? current-mode switching power supplies ? control of high current fet drivers ? motor speed and direction control tm pin configurations is7-1845asrh, is7-1845aseh (8 ld cdip2-t8 sbdip) top view is9-1845asrh, is9-1845aseh (18 ld flatpack) top view notes: 1. grounding the comp pin does not inhibit the output. the outp ut may be inhibited by applying >1.2v to the isense pin. 2. this part should be operated with c t = 3.3nf and r t = 10k timing components only. comp vfb isense rtct 1 2 3 4 8 7 6 5 vref vcc out gnd comp vfb nc nc nc isense rtct nc 3 4 5 6 7 8 9 217 16 15 14 13 12 11 10 vref vcc vc out nc gnd oscgnd nc nc 1 18 nc n o t r e c o m m e n d e d f o r n e w d e s i g n s r e c o m m e n d e d r e p l a c e m e n t p a r t i s l 7 8 8 4 x a r h , i s l 7 8 8 4 x a e h july 13, 2012 fn9001.5
is-1845asrh, IS-1845ASEH 2 fn9001.5 july 13, 2012 ordering information ordering number internal mkt. number temp. range (c) package pkg. dwg. # 5962f0150901v9a is0-1845asrh-q -50 to +125 5962f0150902v9a is0-1845aseh-q -50 to +125 is0-1845asrh/sample is0-1845asrh/sample -50 to +125 5962f0150901vpc is7-1845asrh-q -50 to +125 8 ld sbdip d8.3 5962f0150902vpc is7-1845aseh-q -50 to +125 8 ld sbdip d8.3 5962f0150901vpc is7-1845asrh-qs9000 -50 to +125 8 ld sbdip d8.3 5962f0150901qpc is7-1845asrh-8 -50 to +125 8 ld sbdip d8.3 5962f0150901qpc is7-1845asrh-8s9000 -50 to +125 8 ld sbdip d8.3 5962f0150901vxc is9-1845asrh-q -50 to +125 18 ld flatpack k18.b 5962f0150902vxc is9-1845aseh-q -50 to +125 18 ld flatpack k18.b 5962f0150901vxc is9-1845asrh-qs9000 -50 to +125 18 ld flatpack k18.b 5962f0150901qxc is9-1845asrh-8 -50 to +125 18 ld flatpack k18.b is7-1845asrh/proto is7-1845asrh/proto -50 to +125 8 ld sbdip d8.3 is9-1845asrh/proto is9-1845asrh/proto -50 to +125 18 ld flatpack k18.3 typical performance curves figure 1. oscillator frequency vs r t and c t figure 2. maximum duty cycle vs r t 1 10 100 1 10 100 1k 10k r t timing resistance (k ) frequency (hz) c470pf c1000pf c2200pf c4700pf 0.1 1 10 100 0 20 40 60 80 100 r t timing resistance (k ) d max (%) d max
is-1845asrh, IS-1845ASEH 3 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn9001.5 july 13, 2012 for additional products, see www.intersil.com/product_tree die characteristics die dimensions 3090m x 4080m (121.6 mils x 159.0 mils) thickness: 483m 25.4m (19 mils 1 mil) interface materials glassivation type: phosphorus silicon glass (psg) thickness: 8.0ka 1.0ka top metallization type: alsicu thickness: 16.0ka 2ka substrate radiation hardened silicon gate, dielectric isolation backside finish silicon assembly related information substrate potential unbiased (di) additional information worst case current density <2.0 x 10 5 a/cm 2 transistor count 582 metallization mask layout is-1845asrh notes: 3. both the gnd pads must be bonded to ground. 4. the out double-sized bond pad must be double bonded for current sharing purposes. 5. the oscgnd double-sized bond pad must be double bonded to ground for current sharing purposes. vfb comp vref vc vcc out gnd gnd oscgnd rtct isense
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